• HDL and advantages·
• Levels of abstraction·
• Modules and format·
• Verilog modeling styles·
• Module instantiation·
• Lexical conventions·
• Nets, wire, registers/variables, vectors, arrays and parameter constants·
• Ports and types·
• Verilog operators·
• Functions and Tasks·
• Continuous process, procedural process, events, blocking and non-blocking assignment·
• Tasks, functions and timing control statements·
• Sequential, parallel, branching constructs and Looping constructs·
• Display system tasks·
• Test benches
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